Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 977 of 1513
Aug 12, 2011
20.7 Bit Set/Clear Function
The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface.
An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation,
read/modify/write, or direct writing of target values.
• CAN0 global control register (C0GMCTRL)
• CAN0 global automatic block transmission control register (C0GMABT)
• CAN0 module control register (C0CTRL)
• CAN0 module interrupt enable register (C0IE)
• CAN0 module interrupt status register (C0INTS)
• CAN0 module receive history list register (C0RGPT)
• CAN0 module transmit history list register (C0TGPT)
• CAN0 module time stamp register (C0TS)
• CAN0 message control register (C0MCTRLm)
Remark m = 00 to 31
All the 16 bits in the above registers can be read via the usual method. Use the procedure described in Figure 20-25
below to set or clear the lower 8 bits in these registers.
Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the
bit status after set/clear operation is specified in Figure 20-26). Figure 20-25 shows how the values of set bits or clear bits
relate to set/clear/no change operations in the corresponding register.
Figure 20-25. Example of Bit Setting/Clearing Operations
0000000011010001
0000101111011000
set00001011
0000000000000011
clear 11011000
Set
No change
Clear
Bit status
Register’s current value
Write value
Register’s value after
write operation
Clear
Clear
No change
No change
Set