Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 976 of 1513
Aug 12, 2011
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Set TRQ Clear TRQ Setting of TRQ bit
0 1 TRQ bit is cleared to 0.
1 0 TRQ bit is set to 1.
Other than above TRQ bit is not changed.
Caution Even if the TRQ bit is set (1), transmission may not be immediately executed depending on
the situation such as when a message is received from another node or when a message is
transmitted from the message buffer.
Transmission under execution is not terminated midway even if the TRQ bit is cleared.
Transmission is continued until it is completed (regardless of whether it is executed
successfully or fails).
Set RDY Clear RDY Setting of RDY bit
0 1 RDY bit is cleared to 0.
1 0 RDY bit is set to 1.
Other than above RDY bit is not changed.
Caution Be sure to set the TRQ and RDY bits separately.