Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 97 of 1513
Aug 12, 2011
(2) Accessing specific on-chip peripheral I/O registers
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an
access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is a
possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next instruction
but enters the wait status. If this wait status occurs, the number of clocks required to execute an instruction
increases by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the
wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this
time are shown below.
(1/2)
Peripheral Function Register Name Access k
TAAnCNT Read 1 or 2
Write
• 1st access: No wait
• Continuous write: 0 to 3
TAAnCCR0, TAAnCCR1
Read 1 or 2
Write
• 1st access: No wait
• Continuous write: 0 to 3
16-bit timer/event counter AA (TAA)
(n = 0 to 5, m = 0 to 3, 5)
TAAmIOC4
Read 1 or 2
TABnCNT Read 1 or 2
Write
• 1st access: No wait
• Continuous write: 0 to 3
TABnCCR0 to TABnCCR3
Read 1 or 2
Write
• 1st access: No wait
• Continuous write: 0 to 3
16-bit timer/event counter AB (TAB)
(n = 0, 1)
TABnIOC4
Read 1 or 2
TAB0OPT1 Write
• 1st access: No wait
• Continuous write: 0 to 3
Motor control
TAB0DTC Write
• 1st access: No wait
• Continuous write: 0 to 3
TT0CNT Read 1 or 2
Write
• 1st access: No wait
• Continuous write: 0 to 3
TMT
TT0TCR0, TT0TCR1
Read 1 or 2
Watchdog timer 2 (WDT2) WDTM2
Write
(when WDT2 operating)
3
Real-time output function (RTO) RTBL0, RTBH0
Write
(RTPC0.RTPOE0 bit = 0)
1
ADA0M0 Read 1 or 2
ADA0CR0 to ADA0CR11 Read 1 or 2
A/D converter
ADA0CR0H to ADA0CR11H Read 1 or 2