Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 96 of 1513
Aug 12, 2011
3.4.9 Cautions
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/JG3-H and V850ES/JH3-H.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM) (V850ES/JG3-H only)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related
registers after setting the above registers.
(a) System wait control register (VSWC)
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The V850ES/JG3-
H and V850ES/JH3-H require wait cycles according to the operating frequency. Set the following value to the
VSWC register in accordance with the frequency used.
The VSWC register can be read or written in 8-bit units.
Reset sets this register to 77H.
VSWC
Operating Frequency (f CPU )
f
CPU < 16.6 MHz
16.6 MHz ≤ f
CPU < 25 MHz
25 MHz ≤ f
CPU < 33.3 MHz
33.3 MHz ≤ f
CPU ≤ 48 MHz
Set Value of VSWC
00H
01H
11H
12H
Number of Waits
0 (no waits)
1
2
3
After reset: 77H R/W Address: FFFFF06EH
(b) On-chip debug mode register (OCDM) (V850ES/JG3-H only)
For details, see CHAPTER 32 ON-CHIP DEBUG FUNCTION.
(c) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register to
activate this operation.
For details, see CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2.