Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 959 of 1513
Aug 12, 2011
(11) CAN0 module interrupt status register (C0INTS)
The C0INTS register indicates the interrupt status of the CAN module.
After reset: 0000H R/W Address: 03FEC058H
(a) Read
15 14 13 12 11 10 9 8
C0INTS 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0
(b) Write
15 14 13 12 11 10 9 8
C0INTS 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0
Clear
CINTS5
Clear
CINTS4
Clear
CINTS3
Clear
CINTS2
Clear
CINTS1
Clear
CINTS0
(a) Read
CINTS5 to CINTS0 CAN interrupt status bit
0 No related interrupt source event is generated.
1 A related interrupt source event is generated.
Interrupt status bit Related interrupt source event
CINTS5 Wakeup interrupt from CAN sleep mode
Note
CINTS4 Arbitration loss interrupt
CINTS3 CAN protocol error interrupt
CINTS2 CAN error status interrupt
CINTS1 Interrupt on completion of reception of valid message frame to message buffer m
CINTS0 Interrupt on normal completion of transmission of message frame from message buffer m
Note The CINTS5 bit is set (1) only when the CAN module is woken up from the CAN sleep mode by a CAN
bus operation. The CINTS5 bit is not set (1) when the CAN sleep mode has been released by software.
(b) Write
Clear
CINTS5 to CINTS0
Setting of CINTS5 to CINTS0 bits
0 CINTS5 to CINTS0 bits are not changed.
1 CINTS5 to CINTS0 bits are cleared to 0.
Caution The status bit of this register is not automatically cleared. Clear it (0) by software if each
status must be checked in the interrupt servicing.