Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 952 of 1513
Aug 12, 2011
(3/4)
PSMODE1 PSMODE0 Power save mode
0 0 No power save mode is selected.
0 1 CAN sleep mode
1 0 Setting prohibited
1 1 CAN stop mode
Cautions 1. Transition to and from the CAN stop mode must be made via CAN sleep mode. A request
for direct transition to and from the CAN stop mode is ignored.
2. After releasing the power save mode, the C0GMCTRL.MBON flag must be checked before
accessing the message buffer again.
3. A request for transition to the CAN sleep mode is held pending until it is canceled by
software or until the CAN bus enters the bus idle state. The software can check transition
to the CAN sleep mode by reading the PSMODE0 and PSMODE1 bits.
OPMODE2 OPMODE1 OPMODE0 Operation mode
0 0 0 No operation mode is selected (CAN module is in the initialization mode).
0 0 1 Normal operation mode
0 1 0
Normal operation mode with automatic block transmission function
(normal operation mode with ABT)
0 1 1 Receive-only mode
1 0 0 Single-shot mode
1 0 1 Self-test mode
Other than above Setting prohibited
Caution It may take time to change the mode to the initialization mode or power save mode. Therefore,
be sure to check if the mode has been successfully changed, by reading the register value
before executing the processing.
Remark The OPMODE0 to OPMODE2 bits are read-only in the CAN sleep mode or CAN stop mode.
(b) Write
Set CCERC Setting of CCERC bit
1 CCERC bit is set to 1.
Other than above CCERC bit is not changed.
Set AL Clear AL Setting of AL bit
0 1 AL bit is cleared to 0.
1 0 AL bit is set to 1.
Other than above AL bit is not changed.
Clear VALID Setting of VALID bit
0 VALID bit is not changed.
1 VALID bit is cleared to 0.