Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 950 of 1513
Aug 12, 2011
(6) CAN0 module control register (C0CTRL)
The C0CTRL register is used to control the operation mode of the CAN module.
(1/4)
After reset: 0000H R/W Address: 03FEC050H
(a) Read
15 14 13 12 11 10 9 8
C0CTRL 0 0 0 0 0 0 RSTAT TSTAT
7 6 5 4 3 2 1 0
CCERC AL VALID
PSMODE
1
PSMODE
0
OPMODE
2
OPMODE
1
OPMODE
0
(b) Write
15 14 13 12 11 10 9 8
C0CTRL
Set
CCERC
Set
AL
0
Set
PSMODE
1
Set
PSMODE
0
Set
OPMODE
2
Set
OPMODE
1
Set
OPMODE
0
7 6 5 4 3 2 1 0
0
Clear
AL
Clear
VALID
Clear
PSMODE
1
Clear
PSMODE
0
Clear
OPMODE
2
Clear
OPMODE
1
Clear
OPMODE
0
(a) Read
RSTAT Reception status bit
0 Reception is stopped.
1 Reception is in progress.
Remark • The RSTAT bit is set to 1 under the following conditions (timing)
• The SOF bit of a receive frame is detected
• On occurrence of arbitration loss during a transmit frame
• The RSTAT bit is cleared to 0 under the following conditions (timing)
• When a recessive level is detected at the second bit of the interframe space
• On transition to the initialization mode at the first bit of the interframe space
TSTAT Transmission status bit
0 Transmission is stopped.
1 Transmission is in progress.
Remark • The TSTAT bit is set to 1 under the following conditions (timing)
• The SOF bit of a transmit frame is detected
• The TSTAT bit is cleared to 0 under the following conditions (timing)
• During transition to bus-off status
• On occurrence of arbitration loss in transmit frame
• On detection of recessive level at the second bit of the interframe space
• On transition to the initialization mode at the first bit of the interframe space