Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 949 of 1513
Aug 12, 2011
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• CAN0 module mask 3 register (C0MASK3L, C0MASK3H)
After reset: Undefined R/W Address: C0MASK3L 03FEC048H, C0MASK3H 03FEC04AH
15 14 13 12 11 10 9 8
C0MASK3L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8
7 6 5 4 3 2 1 0
CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0
15 14 13 12 11 10 9 8
C0MASK3H 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24
7 6 5 4 3 2 1 0
CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16
• CAN0 module mask 4 register (C0MASK4L, C0MASK4H)
After reset: Undefined R/W Address: C0MASK4L 03FEC04CH, C0MASK4H 03FEC04EH
15 14 13 12 11 10 9 8
C0MASK4L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8
7 6 5 4 3 2 1 0
CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0
15 14 13 12 11 10 9 8
C0MASK4H 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24
7 6 5 4 3 2 1 0
CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16
CMID28 to CMID0 Mask pattern setting of ID bit
0
The ID bits of the message buffer set by the CMID28 to CMID0 bits are compared with the ID
bits of the received message frame.
1
The ID bits of the message buffer set by the CMID28 to CMID0 bits are not compared with the
ID bits of the received message frame (they are masked).
Caution Be sure to set bits 13 to 15 of the C0MASKaH register to 0.
Remark Masking is always defined by an ID length of 29 bits. If a mask is assigned to a message with a
standard ID, the CMID17 to CMID0 bits are ignored. Therefore, only the CMID28 to CMID18 bits of
the received ID are masked. The same mask can be used for both the standard and extended IDs.