Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 942 of 1513
Aug 12, 2011
(1) CAN0 global control register (C0GMCTRL)
The C0GMCTRL register is used to control the operation of the CAN module.
(1/2)
After reset: 0000H R/W Address: 03FEC000H
(a) Read
15 14 13 12 11 10 9 8
C0GMCTRL MBON 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 EFSD GOM
(b) Write
15 14 13 12 11 10 9 8
C0GMCTRL 0 0 0 0 0 0
Set
EFSD
Set
GOM
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0
Clear
GOM
(a) Read
MBON Bit enabling access to message buffer register, transmit/receive history registers
0
Write access and read access to the message buffer register and the transmit/receive history list registers is
disabled.
1
Write access and read access to the message buffer register and the transmit/receive history list registers is
enabled.
Cautions 1. While the MBON bit is cleared (to 0), software access to the message buffers
(C0MDATA0m, C0MDATA1m, C0MDATA01m, C0MDATA2m, C0MDATA3m, C0MDATA23m,
C0MDATA4m, C0MDATA5m, C0MDATA45m, C0MDATA6m, C0MDATA7m, C0MDATA67m,
C0MDLCm, C0MCONFm, C0MIDLm, C0MIDHm, and C0MCTRLm), or registers related to
transmit history or receive history (C0LOPT, C0TGPT, C0LIPT, and C0RGPT) is disabled.
2. This bit is read-only. Even if 1 is written to the MBON bit while it is 0, the value of the
MBON bit does not change, and access to the message buffer registers, or registers
related to transmit history or receive history remains disabled.
Remark When the CAN sleep mode/CAN stop mode is entered, or when the GOM bit is cleared to 0, the
MBON bit is cleared to 0. When the CAN sleep mode/CAN stop mode is released, or when the GOM
bit is set to 1, the MBON bit is set to 1.