Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 916 of 1513
Aug 12, 2011
(3) Synchronizing data bit
• The receiving node establishes synchronization by a level change on the bus because it does not have a sync
signal.
• The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
(a) Hardware synchronization
This synchronization is established when the receiving node detects the start of frame in the interframe space.
• When a falling edge is detected on the bus, that TQ means the sync segment and the next segment is the
prop segment. In this case, synchronization is established regardless of SJW.
Figure 20-20. Hardware Synchronization Due to Dominant Level Detection During Bus Idle
Start of frameInterframe space
CAN bus
Bit timing
Phase
segment 1
Prop
segment
Sync
segment
Phase
segment 2