Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 914 of 1513
Aug 12, 2011
20.3.7 Baud rate control function
(1) Prescaler
The CAN controller has a prescaler that divides the clock (f
CAN) supplied to CAN. This prescaler generates a CAN
protocol layer base clock (fTQ) that is the CAN module system clock (fCANMOD) divided by 1 to 256 (see 20.6 (12)
CAN0 module bit rate prescaler register (C0BRP)).
(2) Data bit time (8 to 25 time quanta)
One data bit time is defined as shown in Figure 20-18.
1 Time Quanta = 1/f
TQ
The CAN controller sets the data bit time by replacing it with the bit timing parameters such as time segment 1,
time segment 2, and reSynchronization Jump Width (SJW), as shown in Figure 20-18. Time segment 1 is
equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the CAN
protocol specification. Time segment 2 is equivalent to phase segment 2.
Figure 20-18. Segment Setting
Data bit time (DBT)
Phase segment 1
Prop segmentSync segment
Phase segment 2
Time segment 1 (TSEG1)
Time segment 2
(TSEG2)
Sample point (SPT)
Segment name Settable range Notes on setting to conform to CAN specification
Time segment 1 (TSEG1) 2TQ to 16TQ
−
Time segment 2 (TSEG2) 1TQ to 8TQ
IPT of the CAN controller is 0TQ. To conform to the CAN
protocol specification, therefore, a length equal or less to
phase segment 1 must be set here. This means that the
length of time segment 1 minus 1TQ is the settable upper
limit of time segment 2.
reSynchronization Jump Width
(SJW)
1TQ to 4TQ
The length of time segment 1 minus 1TQ or 4TQ,
whichever smaller.
Remark IPT: Information Processing Time
TQ: Time Quanta