Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 910 of 1513
Aug 12, 2011
(b) Error counter
The error counter counts up when an error has occurred, and counts down upon successful transmission and
reception. The error counter counts up immediately after error detection.
Table 20-14. Error Counter
State
Transmission Error Counter
(TEC7 to TEC0 Bits)
Reception Error Counter
(REC6 to REC0 Bits)
Receiving node detects an error (except bit error in the active error
flag or overload flag).
No change +1 (REPS bit = 0)
Receiving node detects dominant level following error flag of error
frame.
No change +8 (REPS bit = 0)
Transmitting node transmits an error flag.
[As exceptions, the error counter does not change in the following
cases.]
<1> ACK error is detected in error passive state and dominant level
is not detected while the passive error flag is being output.
<2> A stuff error is detected in an arbitration field that transmitted a
recessive level as a stuff bit, but a dominant level is detected.
+8 No change
Bit error detection while active error flag or overload flag is being
output (error-active transmitting node)
+8 No change
Bit error detection while active error flag or overload flag is being
output (error-active receiving node)
No change +8 (REPS bit = 0)
When the node detects 14 consecutive dominant-level bits from the
beginning of the active error flag or overload flag, and then
subsequently detects 8 consecutive dominant-level bits.
When the node detects 8 consecutive dominant levels after a
passive error flag
+8 (transmitting) +8 (receiving, REPS bit = 0)
When the transmitting node has completed transmission without
error (±0 if error counter = 0)
–1 No change
When the receiving node has completed reception without error No change
• –1 (1 ≤ REC6 to REC0 ≤
127, REPS bit = 0)
• ±0 (REC6 to REC0 = 0,
REPS bit = 0)
• Any value of 119 to 127
is set (REPS bit = 1)
(c) Occurrence of bit error in intermission
An overload frame is generated.
Caution If an error occurs, it is controlled according to the contents of the transmission error counter
and reception error counter before the error occurred. The value of the error counter is
incremented after the error flag has been output.