Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 905 of 1513
Aug 12, 2011
20.2.5 Overload frame
An overload frame is transmitted under the following conditions.
When the receiving node has not completed the reception operation
Note
If a dominant level is detected at the first two bits during intermission
If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error
delimiter/overload delimiter
Note In this CAN controller, all reception frames can be loaded without outputting an overload frame because of the
enough high-speed internal processing.
Figure 20-16. Overload Frame
<1>
R
D
<2> <3>
6 bits 0 to 6 bits 8 bits
(<4>) (<5>)
Interframe space or overload frame
Overload delimiter
Overload flag (node n)
Overload flag (node m)
Frame
Overload frame
Remark D: Dominant = 0
R: Recessive = 1
Node n node m
Table 20-8. Definition of Overload Frame Fields
No Name Bit Count Definition
<1> Overload flag 6 Outputs 6 dominant-level bits consecutively.
<2> Overload flag from other node 0 to 6
The node that received an overload flag in the interframe space
outputs an overload flag.
<3> Overload delimiter 8
Outputs 8 recessive-level bits consecutively.
If a dominant level is detected at the 8th bit, an overload frame
is transmitted from the next bit.
<4> Frame
Output following an end of frame, error delimiter, or overload
delimiter.
<5>
Interframe space/overload
frame
An interframe space or overload frame starts from here.