Datasheet

4.5.1 Cautions on setting port pins.........................................................................................................172
4.5.2 Cautions on bit manipulation instruction for port n register (Pn)....................................................175
4.5.3 Cautions on on-chip debug pins (V850ES/JG3-H only) ................................................................176
4.5.4 Cautions on P56/INTP05/DRST pin..............................................................................................176
4.5.5 Cautions on P10, P11, and P53 pins when power is turned on ....................................................176
4.5.6 Hysteresis characteristics .............................................................................................................176
CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 177
5.1 Features .................................................................................................................................. 177
5.2 Bus Control Pins .................................................................................................................... 178
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed....................179
5.2.2 Pin status in each operation mode................................................................................................179
5.3 Memory Block Function ........................................................................................................ 180
5.4 Bus Access............................................................................................................................. 181
5.4.1 Number of clocks for access.........................................................................................................181
5.4.2 Bus size setting function ...............................................................................................................181
5.4.3 Access by bus size .......................................................................................................................182
5.5 Wait Function.......................................................................................................................... 189
5.5.1 Programmable wait function..........................................................................................................189
5.5.2 External wait function....................................................................................................................190
5.5.3 Relationship between programmable wait and external wait.........................................................191
5.5.4 Programmable address wait function............................................................................................192
5.6 Idle State Insertion Function................................................................................................. 193
5.7 Bus Hold Function (V850ES/JH3-H only)............................................................................. 194
5.7.1 Functional outline..........................................................................................................................194
5.7.2 Bus hold procedure.......................................................................................................................195
5.7.3 Operation in power save mode .....................................................................................................195
5.8 Bus Priority ............................................................................................................................. 196
5.9 Bus Timing.............................................................................................................................. 197
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 200
6.1 Overview ................................................................................................................................. 200
6.2 Configuration.......................................................................................................................... 201
6.3 Registers ................................................................................................................................. 203
6.4 Operation ................................................................................................................................ 208
6.4.1 Operation of each clock ................................................................................................................208
6.4.2 Clock output function ....................................................................................................................208
6.5 PLL Function .......................................................................................................................... 209
6.5.1 Overview.......................................................................................................................................209
6.5.2 Registers.......................................................................................................................................209
6.5.3 Usage ...........................................................................................................................................212
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA).............................................................. 213
7.1 Overview ................................................................................................................................. 213
7.2 Functions ................................................................................................................................ 213
7.3 Configuration.......................................................................................................................... 214
7.3.1 Pin configuration ...........................................................................................................................216
7.4 Registers ................................................................................................................................. 217
7.5 Operation ................................................................................................................................ 234
7.5.1 Interval timer mode (TAAmMD2 to TAAmMD0 bits = 000) ...........................................................240
7.5.2 External event count mode (TAAnMD2 to TAAnMD0 bits = 001)..................................................250
7.5.3 External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010) .....................................258
7.5.4 One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011)...............................................270
7.5.5 PWM output mode (TAAnMD2 to TAAnMD0 bits = 100) ..............................................................277
7.5.6 Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101).....................................................286
7.5.7 Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110) .........................................303
7.5.8 Timer output operations ................................................................................................................308
7.6 Timer-Tuned Operation Function ......................................................................................... 309