Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 888 of 1513
Aug 12, 2011
Figure 19-23. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (3/3)
(c) Stop condition
IICn
ACKDn
STDn
SPDn
WTIMn
H
H
L
L
L
L
H
H
L
ACKEn
MSTSn
STTn
SPTn
WRELn
INTIICn
TRCn
IICn
ACKDn
STDn
SPDn
WTIMn
ACKEn
MSTSn
STTn
SPTn
WRELn
INTIICn
TRCn
SCL0n
SDA0n
123456789 21
D7 D6 D5 D4 D3 D2 D1 D0 AD5AD6
IICn ← data Note 1 IICn ← address
IICn ← FFH Note2 IICn ← FFH Note2
Note 2 Note 2
(when SPIEn = 1)
ACK
Processing by master device
Transmit
(when SPIEn = 1)
Transfer lines
Processing by slave device
Stop
condition
Start
condition
Receive
Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn.
2. To cancel the slave wait state, write FFH to IICn or set WRELn.
Remark n = 0 to 2