Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 886 of 1513
Aug 12, 2011
Figure 19-23. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
(a) Start condition ~ address
IICn
ACKDn
STDn
SPDn
WTIMn
H
H
L
L
L
L
H
H
L
L
ACKEn
MSTSn
STTn
SPTn
WRELn
INTIICn
TRCn
IICn
ACKDn
STDn
SPDn
WTIMn
ACKEn
MSTSn
STTn
SPTn
WRELn
INTIICn
TRCn
SCL0n
SDA0n
Processing by master device
Transfer lines
Processing by slave device
123456789 4321
AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4D5D6D7
IICn ← address IICn ← data Note 1
IICn ← FFH Note 2
Transmit
Start condition
Receive
Note 2
Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn.
2. To cancel the slave wait state, write FFH to IICn or set WRELn.
Remark n = 0 to 2