Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
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C BUS
R01UH0042EJ0500 Rev.5.00 Page 868 of 1513
Aug 12, 2011
19.9 Address Match Detection Method
In I
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C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address has
been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the
master device, or when an extension code has been received (n = 0 to 2).
19.10 Error Detection
In I
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C bus mode, the status of the serial data bus pin (SDA0n) during data transmission is captured by the IICn register
of the transmitting device, so the data of the IICn register prior to transmission can be compared with the transmitted IICn
data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match (n = 0 to 2).
19.11 Extension Code
(1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (IICSn.EXCn bit) is
set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth
clock (n = 0 to 2).
The local address stored in the SVAn register is not affected.
(2) If 11110xx0 is set to the SVAn register by a 10-bit address transfer and 11110xx0 is transferred from the master
device, the results are as follows. Note that the INTIICn signal occurs at the falling edge of the eighth clock (n = 0
to 2)
• Higher four bits of data match: EXCn bit = 1
• Seven bits of data match: IICSn.COIn bit = 1
(3) Since the processing after the interrupt request signal occurs differs according to the data that follows the
extension code, such processing is performed by software.
For example, when operation as a slave is not desired after the extension code is received, set the IICCn.LRELn
bit to 1 and the CPU will enter the next communication wait state.
Table 19-4. Extension Code Bit Definitions
Slave Address R/W Bit Description
0000 000 0 General call address
1111 0xx 0 10-bit slave address specification (when the address is authorized)
1111 0xx 1 10-bit slave address specification (after the address match, the read
command is issued)
Remark For the expansion codes other than the above, see I
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C bus specifications issued by NXP.