Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 845 of 1513
Aug 12, 2011
19.6.7 Wait state cancellation method
In the case of I
2
C0n, a wait state can be canceled normally in the following ways (n = 0 to 2).
• By writing data to the IICn register
• By setting the IICCn.WRELn bit to 1 (wait state cancellation)
• By setting the IICCn.STTn bit to 1 (start condition generation)
• By setting the IICCn.SPTn bit to 1 (stop condition generation)
If any of these wait state cancellation actions is performed, I
2
C0n will cancel the wait state and restart communication.
When canceling the wait state and sending data (including address), write data to the IICn register.
To receive data after canceling the wait state, or to complete data transmission, set the WRELn bit to 1.
To generate a restart condition after canceling the wait state, set the STTn bit to 1.
To generate a stop condition after canceling the wait state, set the SPTn bit to 1.
Execute cancellation only once for each wait state.
For example, if data is written to the IICn register following wait state cancellation by setting the WRELn bit to 1, a
conflict between the SDA0n line change timing and IICn register write timing may result in the data output to SDA0n being
an incorrect value.
Even in other operations, if communication is stopped halfway, clearing the IICCn.IICEn bit to 0 will stop communication,
enabling the wait state to be cancelled.
If the I
2
C bus dead-locks due to noise, etc., setting the IICCn.LRELn bit to 1 causes the communication operation to be
exited, enabling the wait state to be cancelled.