Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 844 of 1513
Aug 12, 2011
Figure 19-13. Wait State (2/2)
(b) When master and slave devices are both in a nine-clock wait state
(master: transmission, slave: reception, and ACKEn bit = 1)
SCL0n
6
SDA0n
789 123
SCL0n
IICn
6
H
78 1 23
D2 D1 D0 ACK D7 D6 D5
9
IICn
SCL0n
ACKEn
Master
Master and slave both wait
after output of ninth clock.
IICn data write (cancel wait state)
Slave
FFH is written to IICn register
or WRELn bit is set to 1.
Generate according to previously set ACKEn bit value
Transfer lines
Wait state
from master/
slave
Wait state
from slave
Remark n = 0 to 2
A wait state may be automatically generated depending on the setting of the IICCn.WTIMn bit (n = 0 to 2).
Normally, the receiving side cancels the wait state when the IICCn.WRELn bit is set to 1 or when FFH is written to the
IICn register and the transmitting side cancels the wait state when data is written to the IICn register.
The master device can also cancel the wait state via either of the following methods.
• By setting the IICCn.STTn bit to 1
• By setting the IICCn.SPTn bit to 1