Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 842 of 1513
Aug 12, 2011
19.6.5 Stop condition
When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition (n = 0
to 2).
A stop condition is generated when serial transfer from the master device to the slave device has been completed.
When the V850ES/JG3-H or V850ES/JH3-H is used as the slave device, it can detect the stop condition.
Figure 19-12. Stop Condition
H
SCL0n
SDA0n
Remark n = 0 to 2
A stop condition is generated when the IICCn.SPTn bit is set to 1. When the stop condition is detected, the
IICSn.SPDn bit is set to 1 and the interrupt request signal (INTIICn) is generated when the IICCn.SPIEn bit is set to 1 (n =
0 to 2).