Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 839 of 1513
Aug 12, 2011
19.6.2 Addresses
The 7 bits of data that follow the start condition are defined as an address.
An address is a 7-bit data segment that is output so that the master device can select one of the slave devices that are
connected to the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
The slave devices detect via hardware the start condition and check whether or not the 7-bit address data matches the
data values stored in the SVAn register. If the address data matches the values of the SVAn register, the slave device is
selected and communicates with the master device until the master device generates a start condition or stop condition (n
= 0 to 2).
Figure 19-9. Address
Address
SCL0n
1
SDA0n
INTIICn
Note
23456789
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W
Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received
during slave device operation.
Remark n = 0 to 2
An address is output when the slave address and the transfer direction described in 19.6.3 Transfer direction
specification are written together to the IICn registers as eight bits of data. Received addresses are written to the IICn
register (n = 0 to 2).
The slave address is assigned to the higher 7 bits of the IICn register.