Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 838 of 1513
Aug 12, 2011
19.6 I
2
C Bus Definitions and Control Methods
The following section describes the I
2
C bus’s serial data communication format and the signals used by the I
2
C bus.
The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition”
generated on the I
2
C bus’s serial data bus is shown below.
Figure 19-7. I
2
C Bus Serial Data Transfer Timing
1 to 7 8 9 1 to 8 9 1 to 8 9
SCL0n
SDA0n
R/WStart
condition
Address ACK Data Data Stop
condition
ACK ACK
The master device generates the start condition, slave address, and stop condition.
ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8-bit
data).
The serial clock (SCL0n) is continuously output by the master device. However, in the slave device, the SCL0n pin’s
low-level period can be extended and a wait state can be inserted (n = 0 to 2).
19.6.1 Start condition
A start condition is met when the SCL0n pin is high level and the SDA0n pin changes from high level to low level. The
start condition for the SCL0n and SDA0n pins is a signal that the master device outputs to the slave device when starting a
serial transfer. The slave device can detect the start condition (n = 0 to 2).
Figure 19-8. Start Condition
H
SCL0n
SDA0n
A start condition is output when the IICCn.STTn bit is set (1) after a stop condition has been detected (IICSn.SPDn bit =
1). When a start condition is detected, the IICSn.STDn bit is set (1) (n = 0 to 2).
Caution When the IICCn.IICEn bit of the V850ES/JG3-H and V850ES/JH3-H is set to 1 while other devices are
communicating, the start condition may be detected depending on the status of the communication
line. Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level.