Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 835 of 1513
Aug 12, 2011
(7) IIC division clock select registers 0, 1 (OCKS0, OCKS1)
The OCKSm registers control the I
2
C0n division clock (n = 0 to 2, m = 0, 1).
These registers control the I
2
C00 division clock via the OCKS0 register and the I
2
C01 and I
2
C02 division clocks via
the OCKS1 register.
These registers can be read or written in 8-bit units.
Reset sets these registers to 00H.
0OCKSm
(m = 0, 1)
00 OCKSENm OCKSTHm 0 OCKSm1 OCKSm0
After reset: 00H R/W Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H
Stops I
2
C division clock operation
Enables I
2
C division clock operation
OCKSENm
0
1
Operation setting of I
2
C division clock
OCKSm1
0
0
1
1
0
OCKSm0
0
1
0
1
0
Selection of I
2
C division clock
f
XX /4
f
XX /6
f
XX /8
f
XX /10
f
XX /2
OCKSTHm
0
0
0
0
1
(8) IIC shift registers 0 to 2 (IIC0 to IIC2)
The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock.
These registers can be read or written in 8-bit units, but data should not be written to the IICn registers during a
data transfer.
Access (read/write) the IICn registers only during the wait period. Accessing these registers in communication
states other than the wait period is prohibited. However, for the master device, the IICn registers can be written
once only after the transmission trigger bit (IICCn.STTn bit) has been set to 1.
A wait state is released by writing the IICn registers during the wait period, and data transfer is started (n = 0 to 2).
Reset sets these registers to 00H.
After reset: 00H R/W Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H, IIC2 FFFFFDA0H
7 6 5 4 3 2 1 0
IICn
(n = 0 to 2)