Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 833 of 1513
Aug 12, 2011
(5) IIC function expansion registers 0 to 2 (IICX0 to IICX2)
The IICXn registers set I
2
C0n function expansion (valid only in the high-speed mode).
These registers can be read or written in 8-bit or 1-bit units.
Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register and
the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 19.4 (6) I
2
C0n transfer clock setting
method) (m = 0, 1).
Set the IICXn registers when the IICCn.IICEn bit = 0.
Reset sets these registers to 00H.
IICXn
(n = 0 to 2)
After reset: 00H R/W Address: IICX0 FFFFFD85H, IICX1 FFFFFD95H, IICX2 FFFFFDA5H
0 0 0 0 0 0 0 CLXn
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(6) I
2
C0n transfer clock setting method
The I
2
C0n transfer clock frequency (fSCL) is calculated using the following expression (n = 0 to 2).
f
SCL = 1/(m × T + tR + tF)
m = 24, 48, 72, 96, 108, 120, 144, 172, 192, 240, 264, 344, 352, 396, 440, 516, 688, 860 (see Table 19-2
Clock Settings).
T: 1/f
XX
t
R: SCL0n pin rise time
t
F: SCL0n pin fall time
For example, the I
2
C0n transfer clock frequency (fSCL) when fXX = 19.2 MHz, m = 198, tR = 200 ns, and tF = 50 ns is
calculated using following expression.
f
SCL = 1/(198 × 52 ns + 200 ns + 50 ns) ≅ 94.7 kHz
m × T + t R + t F
m/2 × T
t
F
t R
m/2 × T
SCL0n
SCL0n inversion
SCL0n inversion
SCL0n inversion
The clock to be selected can be set by combining of the SMCn, CLn1, and CLn0 bits of the IICCLn register, the
CLXn bit of the IICXn register, and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (n = 0 to 2,
m = 0, 1).