Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 832 of 1513
Aug 12, 2011
(4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2)
The IICCLn registers set the transfer clock for I
2
C0n.
These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only.
Set the IICCLn registers when the IICCn.IICEn bit = 0.
The SMCn, CLn1, and CLn0 bits are set by combining the IICXn.CLXn bit and the OCKSTHm, OCKSm1, and
OCKSm0 bits of the OCKSm register (see 19.4 (6) I
2
C0n transfer clock setting method) (n = 0 to 2, m = 0, 1).
Reset sets these registers to 00H.
After reset: 00H R/W
Note
Address: IICCL0 FFFFFD84H, IICCL1 FFFFFD94H, IICCL2 FFFFFDA4H
7 6 <5> <4> 3 2 1
0
IICCLn 0 0 CLDn DADn SMCn DFCn CLn1 CLn0
(n = 0 to 2)
CLDn Detection of SCL0n pin level (valid only when IICCn.IICEn bit = 1)
0 The SCL0n pin was detected at low level.
1 The SCL0n pin was detected at high level.
Condition for clearing (CLDn bit = 0) Condition for setting (CLDn bit = 1)
• When the SCL0n pin is at low level
• When the IICEn bit = 0 (operation stop)
• After reset
• When the SCL0n pin is at high level
DADn Detection of SDA0n pin level (valid only when IICEn bit = 1)
0 The SDA0n pin was detected at low level.
1 The SDA0n pin was detected at high level.
Condition for clearing (DADn bit = 0) Condition for setting (DAD0n bit = 1)
• When the SDA0n pin is at low level
• When the IICEn bit = 0 (operation stop)
• After reset
• When the SDA0n pin is at high level
SMCn Operation mode switching
0 Operation in standard mode.
1 Operation in high-speed mode.
DFCn Digital filter operation control
0 Digital filter off.
1 Digital filter on.
The digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary according to the DFCn bit setting (on/off).
The digital filter is used to eliminate noise in high-speed mode.
Note Bits 4 and 5 are read-only bits.
Caution Be sure to clear bits 7 and 6 to “0”.
Remark When the IICCn.IICEn bit = 0, 0 is read when reading the CLDn and DADn bits.