Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I

C BUS

R01UH0042EJ0500 Rev.5.00 Page 829 of 1513

Aug 12, 2011

(3/3)

STDn Start condition detection

0 Start condition was not detected.

1 Start condition was detected. This indicates that the address transfer period is in effect

Condition for clearing (STDn bit = 0) Condition for setting (STDn bit = 1)

• When a stop condition is detected

• At the rising edge of the next byte’s first clock

following address transfer

• Cleared by LRELn bit = 1 (communication save)

• When the IICEn bit changes from 1 to 0 (operation

stop)

• After reset

• When a start condition is detected

SPDn Stop condition detection

0 Stop condition was not detected.

1 Stop condition was detected. The master device’s communication is terminated and the bus is

released.

Condition for clearing (SPDn bit = 0) Condition for setting (SPDn bit = 1)

• At the rising edge of the address transfer byte’s first

clock following setting of this bit and detection of a

start condition

• When the IICEn bit changes from 1 to 0 (operation

stop)

• After reset

• When a stop condition is detected

Remark n = 0 to 2