Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 827 of 1513
Aug 12, 2011
(2) IIC status registers 0 to 2 (IICS0 to IICS2)
The IICSn registers indicate the status of I
2
C0n (n = 0 to 2).
These registers are read-only, in 8-bit or 1-bit units. However, the IICSn registers can only be read when the
IICCn.STTn bit is 1 or during the wait period.
Reset sets these registers to 00H.
Caution Accessing the IICSn registers is prohibited in the following statuses. For details, see 3.4.8 (2)
Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
(1/3)
After reset: 00H R Address: IICS0 FFFFFD86H, IICS1 FFFFFD96H, IICS2 FFFFFDA6H
<7> <6> <5> <4> <3> <2> <1> <0>
IICSn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
(n = 0 to 2)
MSTSn Master device status
0 Slave device status or communication standby status
1 Master device communication status
Condition for clearing (MSTSn bit = 0) Condition for setting (MSTSn bit = 1)
• When a stop condition is detected
• When the ALDn bit = 1 (arbitration loss)
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
stop)
• After reset
• When a start condition is generated
ALDn Arbitration loss detection
0 This status means either that there was no arbitration or that the arbitration result was a “win”.
1 This status indicates the arbitration result was a “loss”. The MSTSn bit is cleared to 0.
Condition for clearing (ALDn bit = 0) Condition for setting (ALDn bit = 1)
• Automatically cleared after the IICSn register is
read
Note
• When the IICEn bit changes from 1 to 0 (operation
stop)
• After reset
• When the arbitration result is a “loss”.
EXCn Detection of extension code reception
0 Extension code was not received.
1 Extension code was received.
Condition for clearing (EXCn bit = 0)
Condition for setting (EXCn bit = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
stop)
• After reset
• When the higher four bits of the received address
data are either “0000” or “1111” (set at the rising
edge of the eighth clock).
Note This bit is also cleared when a bit manipulation instruction is executed for another bit in the IICSn
register.