Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 822 of 1513
Aug 12, 2011
19.4 Registers
I
2
C00 to I
2
C02 are controlled by the following registers.
• IIC control registers 0 to 2 (IICC0 to IICC2)
• IIC status registers 0 to 2 (IICS0 to IICS2)
• IIC flag registers 0 to 2 (IICF0 to IICF2)
• IIC clock select registers 0 to 2 (IICCL0 to IICCL2)
• IIC function expansion registers 0 to 2 (IICX0 to IICX2)
• IIC division clock select registers 0, 1 (OCKS0, OCKS1)
The following registers are also used.
• IIC shift registers 0 to 2 (IIC0 to IIC2)
• Slave address registers 0 to 2 (SVA0 to SVA2)
Remark For the alternate-function pin settings, see Table 4-20 Settings When Port Pins Are Used for Alternate
Functions.
(1) IIC control registers 0 to 2 (IICC0 to IICC2)
The IICCn registers enable/stop I
2
C0n operations, set the wait timing, and set other I
2
C operations (n = 0 to 2).
These registers can be read or written in 8-bit or 1-bit units. However, set the SPIEn, WTIMn, and ACKEn bits
when the IICEn bit is 0 or during the wait period. When changing the IICEn bit from “0” to “1”, these bits can also
be set at the same time.
Reset sets these registers to 00H.