Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I
2
C BUS
R01UH0042EJ0500 Rev.5.00 Page 821 of 1513
Aug 12, 2011
(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIICn).
An I
2
C interrupt is generated by either of the following two triggers.
• The falling edge of the eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit)
• Interrupt occurrence due to stop condition detection (set by IICCn.SPIEn bit)
Remark n = 0 to 2
(8) Serial clock controller
In master mode, this circuit generates the clock output via the SCL0n pin from the sampling clock (n = 0 to 2).
(9) Serial clock wait controller
This circuit controls the wait timing.
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits are used to generate and detect various statuses.
(11) Data hold time correction circuit
This circuit generates the hold time for the data corresponding to the falling edge of the SCL0n pin.
(12) Start condition generator
This circuit generates a start condition when the IICCn.STTn bit is set.
However, when in the communication reservation disabled status (IICFn.IICRSVn bit = 1) and when the bus is not
released (IICFn.IICBSYn bit = 1), this request is ignored and the IICFn.STCFn bit is set to 1.
(13) Stop condition generator
This circuit generates a stop condition when the IICCn.SPTn bit is set.
(14) Bus status detector
This circuit detects whether the bus is released by detecting a start condition and stop condition.
However, the bus status cannot be detected immediately after operation, so set the bus status detector to the
initial status by using the IICFn.STCENn bit.