Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)

R01UH0042EJ0500 Rev.5.00 Page 813 of 1513

Aug 12, 2011

18.9 Cautions

(1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if

an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the

CFnSTR.CFnOVE bit after DMA transfer has been completed.

(2) If a register that is prohibited to be rewritten during operation (CFnCTL0.CFnPWR bit = 1) is rewritten by mistake

during operation, set the CFnCTL0.CFnPWR bit to 0 once, then initialize CSIFn.

Registers to which rewriting during operation is prohibited are shown below.

• CFnCTL0 register: CFnTXE, CFnRXE, CFnDIR, CFnTMS bits

• CFnCTL1 register: CFnCKP, CFnDAP, CFnCKS2 to CFnCKS0 bits

• CFnCTL2 register: CFnCL3 to CFnCL0 bits

(3) In communication type 2 or 4 (CFnCTL1.CFnDAP bit = 1), the CFnSTR.CFnTSF bit is cleared half a SCKFn clock

after the occurrence of a reception completion interrupt (INTCFnR).

In the single transfer mode, writing the next transmit data is ignored during communication (CFnTSF bit = 1), and

the next communication is not started. Also if reception-only communication (CFnCTL0.CFnTXE bit = 0,

CFnCTL0.CFnRXE bit = 1) is set, the next communication is not started even if the receive data is read during

communication (CFnTSF bit = 1).

Therefore, when using the single transfer mode with communication type 2 or 4 (CFnDAP bit = 1), pay particular

attention to the following.

• To start the next transmission, confirm that CFnTSF bit = 0 and then write the transmit data to the CFnTX

• To perform the next reception continuously when reception-only communication (CFnTXE bit = 0, CFnRXE bit =

1) is set, confirm that CFnTSF bit = 0 and then read the CFnRX register.

Or, use the continuous transfer mode instead of the single transfer mode. Use of the continuous transfer mode is

recommended especially when using DMA.

Remark n = 0 to 4