Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 811 of 1513
Aug 12, 2011
18.8 Baud Rate Generator
The BRG1 to BRG3 baud rate generators are connected to CSIF0 to CSIF4 as shown in the following block diagram.
CSIF0
CSIF1
CSIF2
CSIF3
CSIF4
BRG1
BRG2
BRG3
f XX
f XX
f XX
f BRG1
f BRG2
f BRG3
(1) Prescaler mode registers 1 to 3 (PRSM1 to PRSM3)
The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIF.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
0PRSMm
(m = 1 to 3)
0 0 BGCEm 0 0 BGCSm1 BGCSm0
Disabled
Enabled
BGCEm
0
1
Baud rate output
f XX
f XX /2
f
XX /4
f
XX /8
Setting value (k)
0
1
2
3
BGCSm1
0
0
1
1
BGCSm0
0
1
0
1
Input clock selection (f
BGCSm )
After reset: 00H R/W Address: PRSM1 FFFFF320H, PRSM2 FFFFF324H,
PRSM3 FFFFF328H
< >
Cautions 1. Do not rewrite the PRSMm register during operation.
2. Set the PRSMm register before setting the BGCEm bit to 1.
2. Be sure to set bits 7 to 5, 3, and 2 to “0”.