Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 810 of 1513
Aug 12, 2011
18.7 Output Pins
(1) SCKFn pin
When CSIFn operation is disabled (CFnCTL0.CFnPWR bit = 0), the SCKFn pin output status is as follows.
CFnCKP CFnCKS2 CFnCKS1 CFnCKS0 SCKFn Pin Output
1 1 1 High impedance 0
Other than above Fixed to high level
1 1 1 High impedance 1
Other than above Fixed to low level
Remarks 1. The output level of the SCKFn pin changes if any of the CFnCTL1.CFnCKP or CFnCKS2 to
CFnCKS0 bits is rewritten.
2. n = 0 to 4
(2) SOFn pin
When CSIFn operation is disabled (CFnPWR bit = 0), the SOFn pin output status is as follows.
CFnTXE CFnDAP CFnDIR SOFn Pin Output
0
× ×
Fixed to low level
0
×
SOFn latch value (low level)
0 CFnTX value (MSB)
1
1
1 CFnTX value (LSB)
Remarks 1. The SOFn pin output changes when any one of the
CFnCTL0.CFnTXE, CFnCTL0.CFnDIR or CFnCTL1.CFnDAP bit
is rewritten.
2. ×: Don’t care
3. n = 0 to 4