Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 808 of 1513
Aug 12, 2011
18.6.14 Clock timing
(1/2)
(i) Communication type 1 (CFnCKP and CFnDAP bits = 00)
D6 D5 D4 D3 D2 D1
SCKFn pin
SIFn capture
Reg-R/W
SOFn pin
INTCFnT
interrupt
Note 1
INTCFnR
interrupt
Note 2
CFnTSF bit
D0D7
(ii) Communication type 3 (CFnCKP and CFnDAP bits = 10)
D6 D5 D4 D3 D2 D1 D0D7
SCKFn pin
SIFn capture
Reg-R/W
SOFn pin
INTCFnT
interrupt
Note 1
INTCFnR
interrupt
Note 2
CFnTSF bit
Notes 1. The INTCFnT interrupt is set when the data written to the CFnTX register is transferred to the data
shift register in the continuous transmission or continuous transmission/reception mode. In the
single transmission or single transmission/reception mode, the INTCFnT interrupt request signal is
not generated, but the INTCFnR interrupt request signal is generated upon end of communication.
2. The INTCFnR interrupt occurs if reception is correctly ended and receive data is ready in the CFnRX
register while reception is enabled. In the single mode, the INTCFnR interrupt request signal is
generated even in the transmission mode, upon end of communication.
Caution In single transfer mode, writing to the CFnTX register with the CFnTSF bit set to 1 is ignored.
This has no effect on the operation during transfer.
For example, if the next data is written to the CFnTX register when DMA is started by
generating the INTCFnR signal, the written data is not transferred because the CFnTSF bit is
set to 1.
Use the continuous transfer mode, not the single transfer mode, for such applications.
Remark n = 0 to 4