Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 806 of 1513
Aug 12, 2011
(2/2)
(12) When the clock of the transfer data length set with the CFnCTL2 register is input without writing to the
CFnTX register, the INTCFnR signal is generated. Clear the CFnTSF bit to 0 to end
transmission/reception.
(13) When the INTCFnR signal is generated, read the CFnRX register.
(14) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag.
(15) To release the transmission/reception enable status, write CFnCTL0.CFnPWR bit = 0,
CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0.
Remark n = 0 to 4