Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 805 of 1513
Aug 12, 2011
(2) Operation timing
(1/2)
SCKFn pin
CFnTSF bit
(1)
(2)
(3)
(4) (5)
(6) (7) (8) (9) (10) (11) (13)(15)(12)
SIFn pin
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SOFn pin
INTCFnT signal
INTCFnR signal
SIFn pin capture
timing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (f
CCLK) =
external clock (SCKFn), and slave mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CFnCTL0 register, and select the transmission/reception mode, MSB first, and
continuous transfer mode at the same time as enabling the operation of the communication clock
(f
CCLK).
(4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device
waits for a serial clock input.
(5) When a serial clock is input, output the transmit data to the SOFn pin in synchronization with the serial
clock, and capture the receive data of the SIFn pin.
(6) When transfer of the transmit data from the CFnTX register to the shift register is completed and
writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is
generated.
(7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnT signal
is generated.
(8) When reception of the transfer data length set with the CFnCTL2 register is completed, the reception
completion interrupt request signal (INTCFnR) is generated, and reading of the CFnRX register is
enabled.
(9) When a serial clock is input continuously, continuous transmission/reception is started.
(10) Read the CFnRX register.
(11) When transfer of the transmit data from the CFnTX register to the shift register is completed and
writing to the CFnTX register is enabled, the INTCFnT signal is generated. To end continuous
transmission/reception with the current transmission/reception, do not write to the CFnTX register.
Remark n = 0 to 4