Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 804 of 1513
Aug 12, 2011
(1) Operation flow
START
END
Yes
No
Is receive data
last data?
Yes
No
Write CFnTX register
CFnOVE bit = 0
(CFnSTR)
Read CFnRX register
Read CFnRX register
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← E3H
No
Yes
(1), (2), (3)
(4)
(5)
(7)
(11)
(9)
(7)
(8)
(13)
(12)
(13)
(14)
(15)
(15)
(10)
No
Yes
CFnTSF bit = 0?
(CFnSTR)
Write CFnTX register
Yes
No
Is data being transmitted
last data?
Start transmission/reception
CFnCTL0 register ← 00H
CFnOVE bit = 1?
(CFnSTR)
INTCFnR interrupt
generated?
(6), (11)
No
Yes
INTCFnT interrupt
generated?
(4)
No
Yes
SCKFn pin input
started?
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4