Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 801 of 1513
Aug 12, 2011
(1) Operation flow
START
No
INTCFnR interrupt
generated?
CFnOVE bit = 1?
(CFnSTR)
END
No
Yes
Yes
CFnRX register
dummy read
CFnSCE bit = 0
(CFnCTL0)
CFnOVE bit = 0
(CFnSTR)
Read CFnRX register
Is data being received
last data?
Yes
CFnSCE bit = 0
(CFnCTL0)
Read CFnRX register
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← A3H
Reception start
(1), (2), (3)
(4)
(5)
(4)
(6)
(8)
(9)
(12)
(13)
(13)
No
Read CFnRX register
(9)
(7)
Read CFnRX register
No
Yes
CFnCTL0 register ← 00H
INTCFnR interrupt
generated?
(9)
(10)
(11)
(8)
No
Yes
CFnTSF bit = 0?
(CFnSTR)
No
Yes
SCKFn pin input
started?
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4