Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 797 of 1513
Aug 12, 2011
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(11) The transfer of the transmit data from the CFnTX register to the shift register is completed and the
INTCFnT signal is generated. To end continuous transmission/reception with the current
transmission/reception, do not write to the CFnTX register.
(12) When the next transmit data is not written to the CFnTX register before transfer completion, stop the
serial clock output to the SCKFn pin after transfer completion, and clear the CFnTSF bit to 0.
(13) When the reception error interrupt request signal (INTCFnR) is generated, read the CFnRX register.
(14) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag.
(15) To release the transmission/reception enable status, write CFnCTL0.CFnPWR bit = 0,
CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0.
Remark n = 0 to 4