Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 785 of 1513
Aug 12, 2011
18.6.5 Single transfer mode (slave mode, reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (f
CCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer
data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
Reception completed?
END
Yes
No (7)
CFnRX register
dummy read
CFnSCE bit = 0
(CFnCTL0)
CFnCTL0 register ← 00H
Read CFnRX register
Read CFnRX register
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← A1H
Start reception
No
INTCFnR interrupt
generated?
Yes
No
Yes
(1), (2), (3)
(4)
(5)
(4)
(6)
(6)
(8)
(9)
(10)
SCKFn pin input
started?
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4