Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 784 of 1513
Aug 12, 2011
(2) Operation timing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Bit 0
SCKFn pin
CFnTSF bit
(1)
(2)
(3)
(4) (5) (6) (7) (8)
SOFn pin
INTCFnR signal
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (f
CCLK) =
external clock (SCKFn), and slave mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C1H to the CFnCTL0 register, and select the transmission mode and MSB first at the same time
as enabling the operation of the communication clock (f
CCLK).
(4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device
waits for a serial clock input.
(5) When a serial clock is input, output the transmit data from the SOFn pin in synchronization with the
serial clock.
(6) When transmission of the transfer data length set with the CFnCTL2 register is completed, stop the
serial clock input and transmit data output, generate the reception completion interrupt request signal
(INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0.
(7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnR signal
is generated, and wait for a serial clock input.
(8) To end transmission, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0.
Remark n = 0 to 4