Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 781 of 1513
Aug 12, 2011
18.6.3 Single transfer mode (master mode, transmission/reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (f
CCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =
8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
(4)
(7), (9)
(5)
(6)
(10)
No (8)
Transmission/reception
completed?
END
Yes
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← E1H
Write CFnTX register
Read CFnRX register
Start transmission/reception
CFnCTL0 ← 00H
No
INTCFnR interrupt
generated?
Yes
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4