Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 780 of 1513
Aug 12, 2011
(2) Operation timing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
SCKFn pin
CFnTSF bit
(1)
(2)
(3)
(4) (5) (6) (7) (10)(8)
(9)
SIFn pin
SIFn pin capture
timing
INTCFnR signal
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (f
CCLK) =
f
XX/2 or fXX/3, and master mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A1H to the CFnCTL0 register, and select the reception mode and MSB first at the same time as
enabling the operation of the communication clock (f
CCLK).
(4) Set the CFnSTR.CFnTSF bit to 1 by performing a dummy read of the CFnRX register, and start
reception.
(5) When reception is started, output the serial clock to the SCKFn pin, and capture the receive data of the
SIFn pin in synchronization with the serial clock.
(6) When reception of the transfer data length set with the CFnCTL2 register is completed, stop the serial
clock output and data capturing, generate the reception completion interrupt request signal (INTCFnR)
at the last edge of the serial clock, and clear the CFnTSF bit to 0.
(7) To continue reception, read the CFnRX register while keeping the CFnCTL0.CFnSCE bit = 1 after the
INTCFnR signal is generated.
(8) To read the CFnRX register without starting the next reception, write the CFnSCE bit = 0.
(9) Read the CFnRX register.
(10) To end reception, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0.
Remark n = 0 to 4