Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 777 of 1513
Aug 12, 2011
18.6 Operation
18.6.1 Single transfer mode (master mode, transmission mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (f
CCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =
8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
No
(1), (2), (3)
(4)
(5)
(6)
(8)
No (7)
INTCFnR interrupt
generated?
Transmission
completed?
END
Yes
Yes
CFnCTL1 register ← 00H
CFnCTL2 register ← 00H
CFnCTL0 register ← C1H
Write CFnTX register
Start transmission
CFnCTL0 ← 00H
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4