Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 772 of 1513
Aug 12, 2011
(2) CSIFn control register 1 (CFnCTL1)
CFnCTL1 is an 8-bit register that controls the CSIFn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution The CFnCTL1 register can be rewritten only when the CFnCTL0.CFnPWR bit = 0.
0
CFnCKP
0
0
1
1
Specification of data transmission/
reception timing in relation to SCKFn
CFnCTL1
(n = 0 to 4)
0
CFnDAP
0
1
0
1
0 CFnCKP CFnDAP
CFnCKS2 CFnCKS1 CFnCKS0
After reset: 00H R/W Address: CF0CTL1 FFFFFD01H, CF1CTL1 FFFFFD11H,
CF2CTL1 FFFFFD21H, CF3CTL1 FFFFFD31H,
CF4CTL1 FFFFFD41H
CFnCKS2
0
0
0
0
1
1
1
1
CFnCKS1
0
0
1
1
0
0
1
1
CFnCKS0
0
1
0
1
0
1
0
1
Communication clock (f
CCLK
)
f
XX
/3
f
XX
/4
f
XX
/6
f
XX
/8
f
XX
/32
f
XX
/64
f
BRGm
External clock (SCKFn)
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
Mode
D7 D6 D5 D4 D3 D2 D1 D0
SCKFn (I/O)
SIFn capture
SOFn (output)
D7 D6 D5 D4 D3 D2 D1 D0
SCKFn (I/O)
SIFn capture
SOFn (output)
D7 D6 D5 D4 D3 D2 D1 D0
SCKFn (I/O)
SIFn capture
SOFn (output)
D7 D6 D5 D4 D3 D2 D1 D0
SCKFn (I/O)
SIFn capture
SOFn (output)
Communication
type 1
Communication
type 2
Communication
type 3
Communication
type 4
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
n = 0 to 2, 4
Note 1
n = 3
Note 2
Notes 1. Set the communication clock (f
CCLK) to 8 MHz or lower (master/slave mode).
2. Set the communication clock (f
CCLK) to 12 MHz or lower (master mode) and 8
MHz or lower (master/slave mode).
Remark When n = 0, 1, m = 1
When n = 2, 3, m = 2
When n = 4, m = 3
For details of f
BRGm, see 18.8 Baud Rate Generator.