Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 771 of 1513
Aug 12, 2011
(3/3)
Communication start trigger invalid
Communication start trigger valid
CFnSCE
0
1
Specification of start transfer disable/enable
• In master mode
This bit enables or disables the communication start trigger.
(a) In single transmission or transmission/reception mode, or continuous
transmission or continuous transmission/reception mode
A communication operation can be started by writing data to the CFnTX
register when the CFnSCE bit is 1.
Set the CFnSCE bit to 1.
(b) In single reception mode
Disable starting the next receive operation by clearing the CFnSCE bit to 0
before reading the last receive data, because a receive operation is started by
reading receive data (CFnRX register)
Note 1
.
(c) In continuous reception mode
Clear the CFnSCE bit to 0 one communication clock before reception of the
last data is completed to disable the start of reception after the last data is
received
Note 2
.
• In slave mode
This bit enables or disables the communication start trigger.
Set the CFnSCE bit to 1.
[Usage of CFnSCE bit]
• In single reception mode
<1>When reception of the last data is completed by INTCFnR interrupt
servicing, clear the CFnSCE bit to 0 before reading the CFnRX register.
<2>After confirming the CFnSTR.CFnTSF bit = 0, clear the CFnRXE bit to 0 to
disable reception.
To continue reception, set the CFnSCE bit to 1 to start the next reception
by dummy-reading the CFnRX register.
• In continuous reception mode
<1>Clear the CFnSCE bit to 0 during reception of the last data by INTCFnR
interrupt servicing.
<2>Read the CFnRX register.
<3>Read the last reception data by reading the CFnRX register after
acknowledging the CFnTIR interrupt.
<4>After confirming the CFnSTR.CFnTSF bit = 0, clear the CFnRXE bit to 0 to
disable reception.
To continue reception, set the CFnSCE bit to 1 to wait for the next reception
by dummy-reading the CFnRX register.
Notes 1. If the CFnSCE bit is read while it is 1, the next communication operation is started.
2. The CFnSCE bit is not cleared to 0 one communication clock before the completion
of the last data reception, the next communication operation is automatically
started.
Caution Be sure to clear bits 3 and 2 to “0”.