Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 769 of 1513
Aug 12, 2011
18.4 Registers
The following registers are used to control CSIFn.
• CSIFn control register 0 (CFnCTL0)
• CSIFn control register 1 (CFnCTL1)
• CSIFn control register 2 (CFnCTL2)
• CSIFn status register (CFnSTR)
(1) CSIFn control register 0 (CFnCTL0)
CFnCTL0 is a register that controls the CSIFn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
(1/3)
CFnPWR
Disables CSIFn operation and resets the CFnSTR register
Enables CSIFn operation
CFnPWR
0
1
Specification of CSIFn operation disable/enable
CFnCTL0
(n = 0 to 4)
CFnTXE
Note
CFnRXE
Note
CFnDIR
Note
00 CFnTMS
Note
CFnSCE
After reset: 01H R/W Address: CF0CTL0 FFFFFD00H, CF1CTL0 FFFFFD10H,
CF2CTL0 FFFFFD20H, CF3CTL0 FFFFFD30H,
CF4CTL0 FFFFFD40H
• The CFnPWR bit controls the CSIFn operation and resets the internal circuit.
Disables transmit operation
Enables transmit operation
CFnTXE
Note
0
1
Specification of transmit operation disable/enable
• The SOFn output is low level when the CFnTXE bit is 0.
• No reception completion interrupt is output even when the prescribed data is
transferred, and the receive data (CFnRX register) is not updated, because the
receive operation is disabled by clearing the CFnRXE bit to 0.
Disables receive operation
Enables receive operation
CFnRXE
Note
0
1
Specification of receive operation disable/enable
< >
< >
< > < >
< >
Note These bits can only be rewritten when the CFnPWR bit = 0.
However, CFnPWR bit = 1 can also be set at the same time as
rewriting these bits.
Caution To forcibly suspend transmission/reception, clear the CFnPWR
bit to 0 instead of the CFnRXE and CFnTXE bits.
At this time, the clock output is stopped.