Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
R01UH0042EJ0500 Rev.5.00 Page 766 of 1513
Aug 12, 2011
18.3 Configuration
The following shows the block diagram of CSIFn.
Figure 18-4. Block Diagram of CSIFn
Internal bus
CFnCTL2CFnCTL0
CFnSTR
Controller
INTCFnR
f CCLK
SOFn
INTCFnT
CFnTX
SO latch
Phase
control
Shift register
CFnRX
CFnCTL1
Phase control
SIFn
f BRGm
f XX /3
f
XX /4
f
XX /6
f
XX /8
f
XX /32
f
XX /64
SCKFn
Selector
Note
Note For CSIF3: f
XX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXX/64
Remark f
CCLK: Communication clock
f
XX: Main clock frequency
f
BRGm: Count clock of the baud rate generator
n = 0 to 4
m = 1 (n = 0, 1)
m = 2 (n = 2, 3)
m = 3 (n = 4)