Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 753 of 1513
Aug 12, 2011
17.7 Dedicated Baud Rate Generator
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and
generates a serial clock during transmission and reception with UARTCn. Regarding the serial clock, a dedicated baud
rate generator output can be selected for each channel.
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
Figure 17-19. Configuration of Baud Rate Generator
f UCLK
Selector
UCnPWR
8-bit counter
Match detector Baud rate
UCnCTL2:
UCnBRS7 to UCnBRS0
1/2
UCnPWR, UCnTXEn bits
(or UCnRXE bit)
UCnCTL1:
UCnCKS3 to UCnCKS0
f XX /2
f XX /4
f XX /8
f XX /16
f
XX /32
f XX /64
f XX /128
f
XX /256
f XX /512
f XX /1024
f XX /2048
ASCKC0
Note
Note Only UARTC0 is valid; setting UARTC1 and UARTC4 is prohibited.
Remarks 1. n = 0 to 4
2. f
XX: Main clock frequency
f
UCLK: Base clock frequency
(a) Base clock
When the UCnCTL0.UCnPWR bit is 1, the clock selected by the UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0
bits is supplied to the 8-bit counter. This clock is called the base clock (f
UCLK).
(b) Serial clock generation
A serial clock can be generated by setting the UCnCTL1 register and the UCnCTL2 register (n = 0 to 4).
The base clock is selected by UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits.
The frequency division value for the 8-bit counter can be set using the UCnCTL2.UCnBRS7 to
UCnCTL2.UCnBRS0 bits.