Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 752 of 1513
Aug 12, 2011
17.6.10 Receive data noise filter
This filter samples the RXDCn pin using the base clock of the prescaler output.
When the same sampling value is read twice, the match detector output changes and the RXDCn signal is sampled as
the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit
(see Figure 17-18). See 17.7 (1) (a) Base clock regarding the base clock.
Moreover, since the circuit is as shown in Figure 17-17, the processing that goes on within the receive operation is
delayed by 3 clocks in relation to the external signal status.
Figure 17-17. Noise Filter Circuit
Match
detector
In
Base clock (f
UCLK)
RXDCn
QIn
LD_EN
Q Internal signal C
Internal signal B
In Q
Internal signal A
Figure 17-18. Timing of RXDCn Signal Judged as Noise
Internal signal B
Base clock
RXDCn (input)
Internal signal C
Mismatch
(judged as noise)
Internal signal A
Mismatch
(judged as noise)
Match Match