Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 748 of 1513
Aug 12, 2011
17.6.7 UART reception
The reception wait status is set by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE bit
to 1. In the reception wait status, the RXDCn pin is monitored and start bit detection is performed.
Start bit detection is performed using a two-step detection routine.
First the rising edge of the RXDCn pin is detected and sampling is started at the falling edge. The start bit is
recognized if the RXDCn pin is low level at the start bit sampling point. After a start bit has been recognized, the receive
operation starts, and serial data is saved to the UARTCn receive shift register according to the set baud rate.
When the reception completion interrupt request signal (INTUCnR) is output upon reception of the stop bit, the data of
the UARTCn receive shift register is written to the UCnRX register. However, if an overrun error (UCnSTR.UCnOVE bit)
occurs, the receive data at this time is not written to the UCnRX register and is discarded.
Even if a parity error (UCnSTR.UCnPE bit) or a framing error (UCnSTR.UCnFE bit) occurs during reception, reception
continues until the reception position of the first stop bit, and INTUCnR is output following reception completion.
Figure 17-15. UART Reception
Start
bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
bit
Stop
bit
INTUCnR
RXDCn
UCnRX
Cautions 1. Be sure to read the UCnRX register even when a reception error occurs. If the UCnRX register is
not read, an overrun error occurs during reception of the next data, and reception errors continue
occurring indefinitely.
2. The operation during reception is performed assuming that there is only one stop bit. A second
stop bit is ignored.
3. When reception is completed, read the UCnRX register after the reception completion interrupt
request signal (INTUCnR) has been generated, and clear the UCnPWR or UCnRXE bit to 0. If the
UCnPWR or UCnRXE bit is cleared to 0 before the INTUCnR signal is generated, the read value of
the UCnRX register cannot be guaranteed.
4. If receive completion processing (INTUCnR signal generation) of UARTCn and the UCnPWR bit =
0 or UCnRXE bit = 0 conflict, the INTUCnR signal may be generated in spite of these being no data
stored in the UCnRX register.
To complete reception without waiting for the INTUCnR signal to be generated, be sure to set (1)
the interrupt mask flag (UCnRMK) of the interrupt control register (UCnRIC), clear (0) the UCnPWR
bit or UCnRXE bit, and then clear the interrupt request flag (UCnRIF) of the UCnRIC register.